mesa: Introduce a globally-available minify() macro.

This matches u_minify()'s behavior, for consistency.

Reviewed-by: Brian Paul <brianp@vmware.com>

src/mesa/drivers/dri/i915/i915_tex_layout.c

@@ -172,9 +172,9 @@ i915_miptree_layout_3d(struct intel_mipmap_tree * mt)
 
       stack_height += MAX2(2, height);
 
-      width = minify(width);
-      height = minify(height);
-      depth = minify(depth);
+      width = minify(width, 1);
+      height = minify(height, 1);
+      depth = minify(depth, 1);
    }
 
    /* Fixup depth image_offsets: */
@@ -186,7 +186,7 @@ i915_miptree_layout_3d(struct intel_mipmap_tree * mt)
 					0, i * stack_height);
       }
 
-      depth = minify(depth);
+      depth = minify(depth, 1);
    }
 
    /* Multiply slice size by texture depth for total size.  It's
@@ -219,8 +219,8 @@ i915_miptree_layout_2d(struct intel_mipmap_tree * mt)
 
       mt->total_height += img_height;
 
-      width = minify(width);
-      height = minify(height);
+      width = minify(width, 1);
+      height = minify(height, 1);
    }
 }
 
@@ -447,9 +447,9 @@ i945_miptree_layout_3d(struct intel_mipmap_tree * mt)
 	 pack_y_pitch >>= 1;
       }
 
-      width = minify(width);
-      height = minify(height);
-      depth = minify(depth);
+      width = minify(width, 1);
+      height = minify(height, 1);
+      depth = minify(depth, 1);
    }
 }
 

src/mesa/drivers/dri/i965/brw_tex_layout.c

@@ -48,7 +48,7 @@ brw_miptree_layout_texture_array(struct intel_context *intel,
    int h0, h1, q;
 
    h0 = ALIGN(mt->physical_height0, mt->align_h);
-   h1 = ALIGN(minify(mt->physical_height0), mt->align_h);
+   h1 = ALIGN(minify(mt->physical_height0, 1), mt->align_h);
    if (mt->array_spacing_lod0)
       qpitch = h0;
    else
@@ -131,10 +131,10 @@ brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
 
 
 	 mt->total_height += y;
-	 width  = minify(width);
-	 height = minify(height);
+	 width  = minify(width, 1);
+	 height = minify(height, 1);
 	 if (mt->target == GL_TEXTURE_3D)
-	    depth = minify(depth);
+	    depth = minify(depth, 1);
 
 	 if (mt->compressed) {
 	    pack_y_pitch = (height + 3) / 4;

src/mesa/drivers/dri/intel/intel_tex_layout.c

@@ -170,11 +170,11 @@ void i945_miptree_layout_2d(struct intel_mipmap_tree *mt)
        GLuint mip1_width;
 
        if (mt->compressed) {
-           mip1_width = ALIGN(minify(mt->physical_width0), mt->align_w)
-               + ALIGN(minify(minify(mt->physical_width0)), mt->align_w);
+          mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
+             ALIGN(minify(mt->physical_width0, 2), mt->align_w);
        } else {
-           mip1_width = ALIGN(minify(mt->physical_width0), mt->align_w)
-               + minify(minify(mt->physical_width0));
+          mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
+             minify(mt->physical_width0, 2);
        }
 
        if (mip1_width > mt->total_width) {
@@ -208,7 +208,7 @@ void i945_miptree_layout_2d(struct intel_mipmap_tree *mt)
 	 y += img_height;
       }
 
-      width  = minify(width);
-      height = minify(height);
+      width  = minify(width, 1);
+      height = minify(height, 1);
    }
 }

src/mesa/drivers/dri/intel/intel_tex_layout.h

@@ -32,12 +32,6 @@
 
 #include "main/macros.h"
 
-
-static INLINE GLuint minify( GLuint d )
-{
-   return MAX2(1, d>>1);
-}
-
 extern void i945_miptree_layout_2d(struct intel_mipmap_tree *mt);
 
 void

src/mesa/drivers/dri/nouveau/nouveau_texture.c

@@ -411,8 +411,8 @@ relayout_texture(struct gl_context *ctx, struct gl_texture_object *t)
 			};
 
 			offset += size;
-			width = MAX2(1, width / 2);
-			height = MAX2(1, height / 2);
+			width = minify(width, 1);
+			height = minify(height, 1);
 		}
 
 		/* Get new storage. */

src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c

@@ -147,15 +147,6 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree
 			lvl->rowstride, lvl->width, height, lvl->faces[face].offset);
 }
 
-static GLuint minify(GLuint size, GLuint levels)
-{
-	size = size >> levels;
-	if (size < 1)
-		size = 1;
-	return size;
-}
-
-
 static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
 {
 	GLuint curOffset, i, face, level;

src/mesa/main/macros.h

@@ -656,6 +656,12 @@ INTERP_4F(GLfloat t, GLfloat dst[4], const GLfloat out[4], const GLfloat in[4])
 #define MIN3( A, B, C ) ((A) < (B) ? MIN2(A, C) : MIN2(B, C))
 #define MAX3( A, B, C ) ((A) > (B) ? MAX2(A, C) : MAX2(B, C))
 
+static inline unsigned
+minify(unsigned value, unsigned levels)
+{
+    return MAX2(1, value >> levels);
+}
+
 /**
  * Align a value up to an alignment value
  *