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@@ -126,6 +126,7 @@ void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, |
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void si_need_dma_space(struct si_context *ctx, unsigned num_dw, |
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struct si_resource *dst, struct si_resource *src) |
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{ |
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struct radeon_winsys *ws = ctx->ws; |
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uint64_t vram = ctx->dma_cs->used_vram; |
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uint64_t gtt = ctx->dma_cs->used_gart; |
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@@ -141,11 +142,11 @@ void si_need_dma_space(struct si_context *ctx, unsigned num_dw, |
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/* Flush the GFX IB if DMA depends on it. */ |
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if (radeon_emitted(ctx->gfx_cs, ctx->initial_gfx_cs_size) && |
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((dst && |
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ctx->ws->cs_is_buffer_referenced(ctx->gfx_cs, dst->buf, |
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RADEON_USAGE_READWRITE)) || |
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ws->cs_is_buffer_referenced(ctx->gfx_cs, dst->buf, |
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RADEON_USAGE_READWRITE)) || |
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(src && |
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ctx->ws->cs_is_buffer_referenced(ctx->gfx_cs, src->buf, |
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RADEON_USAGE_WRITE)))) |
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ws->cs_is_buffer_referenced(ctx->gfx_cs, src->buf, |
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RADEON_USAGE_WRITE)))) |
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si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); |
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/* Flush if there's not enough space, or if the memory usage per IB |
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@@ -161,7 +162,7 @@ void si_need_dma_space(struct si_context *ctx, unsigned num_dw, |
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* engine busy while uploads are being submitted. |
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*/ |
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num_dw++; /* for emit_wait_idle below */ |
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if (!ctx->ws->cs_check_space(ctx->dma_cs, num_dw) || |
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if (!ws->cs_check_space(ctx->dma_cs, num_dw) || |
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ctx->dma_cs->used_vram + ctx->dma_cs->used_gart > 64 * 1024 * 1024 || |
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!radeon_cs_memory_below_limit(ctx->screen, ctx->dma_cs, vram, gtt)) { |
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si_flush_dma_cs(ctx, PIPE_FLUSH_ASYNC, NULL); |
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@@ -172,11 +173,11 @@ void si_need_dma_space(struct si_context *ctx, unsigned num_dw, |
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* prevent read-after-write hazards. |
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*/ |
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if ((dst && |
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ctx->ws->cs_is_buffer_referenced(ctx->dma_cs, dst->buf, |
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RADEON_USAGE_READWRITE)) || |
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ws->cs_is_buffer_referenced(ctx->dma_cs, dst->buf, |
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RADEON_USAGE_READWRITE)) || |
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(src && |
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ctx->ws->cs_is_buffer_referenced(ctx->dma_cs, src->buf, |
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RADEON_USAGE_WRITE))) |
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ws->cs_is_buffer_referenced(ctx->dma_cs, src->buf, |
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RADEON_USAGE_WRITE))) |
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si_dma_emit_wait_idle(ctx); |
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if (dst) { |