radeonsi/gfx9: fix MIP0_WIDTH & MIP0_HEIGHT for compressed texture blits

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

src/gallium/drivers/r600/r600_blit.c

@@ -726,7 +726,10 @@ void r600_resource_copy_region(struct pipe_context *ctx,
 		}
 	}
 
-	dst_view = r600_create_surface_custom(ctx, dst, &dst_templ, dst_width, dst_height);
+	dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
+					      /* we don't care about these two for r600g */
+					      dst->width0, dst->height0,
+					      dst_width, dst_height);
 
 	if (rctx->b.chip_class >= EVERGREEN) {
 		src_view = evergreen_create_sampler_view_custom(ctx, src, &src_templ,

src/gallium/drivers/r600/r600_pipe.h

@@ -737,10 +737,6 @@ unsigned r600_tex_wrap(unsigned wrap);
 unsigned r600_tex_mipfilter(unsigned filter);
 unsigned r600_tex_compare(unsigned compare);
 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
-struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
-						struct pipe_resource *texture,
-						const struct pipe_surface *templ,
-						unsigned width, unsigned height);
 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 				   const unsigned char *swizzle_view,
 				   boolean vtx);

src/gallium/drivers/radeon/r600_pipe_common.h

@@ -275,6 +275,10 @@ struct r600_texture {
 struct r600_surface {
 	struct pipe_surface		base;
 
+	/* These can vary with block-compressed textures. */
+	unsigned width0;
+	unsigned height0;
+
 	bool color_initialized;
 	bool depth_initialized;
 
@@ -804,6 +808,7 @@ void vi_dcc_disable_if_incompatible_format(struct r600_common_context *rctx,
 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 						struct pipe_resource *texture,
 						const struct pipe_surface *templ,
+						unsigned width0, unsigned height0,
 						unsigned width, unsigned height);
 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 void vi_separate_dcc_start_query(struct pipe_context *ctx,

src/gallium/drivers/radeon/r600_texture.c

@@ -1862,6 +1862,7 @@ void vi_dcc_disable_if_incompatible_format(struct r600_common_context *rctx,
 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 						struct pipe_resource *texture,
 						const struct pipe_surface *templ,
+						unsigned width0, unsigned height0,
 						unsigned width, unsigned height)
 {
 	struct r600_common_context *rctx = (struct r600_common_context*)pipe;
@@ -1881,6 +1882,9 @@ struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 	surface->base.height = height;
 	surface->base.u = templ->u;
 
+	surface->width0 = width0;
+	surface->height0 = height0;
+
 	if (texture->target != PIPE_BUFFER)
 		vi_dcc_disable_if_incompatible_format(rctx, texture,
 						      templ->u.tex.level,
@@ -1917,7 +1921,9 @@ static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 		}
 	}
 
-	return r600_create_surface_custom(pipe, tex, templ, width, height);
+	return r600_create_surface_custom(pipe, tex, templ,
+					  tex->width0, tex->height0,
+					  width, height);
 }
 
 static void r600_surface_destroy(struct pipe_context *pipe,

src/gallium/drivers/radeonsi/si_blit.c

@@ -845,7 +845,7 @@ void si_resource_copy_region(struct pipe_context *ctx,
 	struct pipe_surface *dst_view, dst_templ;
 	struct pipe_sampler_view src_templ, *src_view;
 	unsigned dst_width, dst_height, src_width0, src_height0;
-	unsigned src_force_level = 0;
+	unsigned dst_width0, dst_height0, src_force_level = 0;
 	struct pipe_box sbox, dstbox;
 
 	/* Handle buffers first. */
@@ -863,6 +863,8 @@ void si_resource_copy_region(struct pipe_context *ctx,
 
 	dst_width = u_minify(dst->width0, dst_level);
 	dst_height = u_minify(dst->height0, dst_level);
+	dst_width0 = dst->width0;
+	dst_height0 = dst->height0;
 	src_width0 = src->width0;
 	src_height0 = src->height0;
 
@@ -881,6 +883,8 @@ void si_resource_copy_region(struct pipe_context *ctx,
 
 		dst_width = util_format_get_nblocksx(dst->format, dst_width);
 		dst_height = util_format_get_nblocksy(dst->format, dst_height);
+		dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
+		dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
 		src_width0 = util_format_get_nblocksx(src->format, src_width0);
 		src_height0 = util_format_get_nblocksy(src->format, src_height0);
 
@@ -904,6 +908,7 @@ void si_resource_copy_region(struct pipe_context *ctx,
 			dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
 
 			dst_width = util_format_get_nblocksx(dst->format, dst_width);
+			dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
 			src_width0 = util_format_get_nblocksx(src->format, src_width0);
 
 			dstx = util_format_get_nblocksx(dst->format, dstx);
@@ -946,6 +951,7 @@ void si_resource_copy_region(struct pipe_context *ctx,
 
 	/* Initialize the surface. */
 	dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
+					      dst_width0, dst_height0,
 					      dst_width, dst_height);
 
 	/* Initialize the sampler view. */

src/gallium/drivers/radeonsi/si_state.c

@@ -2227,8 +2227,8 @@ static void si_initialize_color_surface(struct si_context *sctx,
 		surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
 		surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
 					 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
-		surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(rtex->resource.b.b.width0 - 1) |
-					 S_028C68_MIP0_HEIGHT(rtex->resource.b.b.height0 - 1) |
+		surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
+					 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
 					 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
 	}
 
@@ -3315,7 +3315,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
 	height = height0;
 	depth = texture->depth0;
 
-	if (force_level) {
+	if (sctx->b.chip_class <= VI && force_level) {
 		assert(force_level == first_level &&
 		       force_level == last_level);
 		base_level = force_level;