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@@ -72,7 +72,7 @@ void r300_emit_invariant_state(struct r300_context* r300) |
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END_CS; |
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/* XXX unsorted stuff from surface_fill */ |
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BEGIN_CS(75 + (caps->has_tcl ? 5 : 0)); |
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BEGIN_CS(71 + (caps->has_tcl ? 5 : 0) + (caps->is_r500 ? 4 : 0)); |
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/* Flush PVS. */ |
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OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0); |
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@@ -115,8 +115,10 @@ void r300_emit_invariant_state(struct r300_context* r300) |
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OUT_CS_REG(R300_RB3D_CCTL, 0x00000000); |
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OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F); |
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OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000); |
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OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000); |
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OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF); |
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if (caps->is_r500) { |
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OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000); |
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OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF); |
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} |
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OUT_CS_REG(R300_ZB_FORMAT, 0x00000002); |
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OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003); |
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OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000); |