radeonsi: emit_cb_render_state packets optimization

Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

src/gallium/drivers/radeonsi/si_build_pm4.h

@@ -153,4 +153,32 @@ static inline void radeon_opt_set_context_reg2(struct si_context *sctx, unsigned
 	}
 }
 
+/**
+ * Set 3 consecutive registers if any registers value is different.
+ */
+static inline void radeon_opt_set_context_reg3(struct si_context *sctx, unsigned offset,
+					       enum si_tracked_reg reg, unsigned value1,
+					       unsigned value2, unsigned value3)
+{
+	struct radeon_winsys_cs *cs = sctx->gfx_cs;
+
+	if (!(sctx->tracked_regs.reg_saved & (1 << reg)) ||
+	    !(sctx->tracked_regs.reg_saved & (1 << (reg + 1))) ||
+	    !(sctx->tracked_regs.reg_saved & (1 << (reg + 2))) ||
+	    sctx->tracked_regs.reg_value[reg] != value1 ||
+	    sctx->tracked_regs.reg_value[reg+1] != value2 ||
+	    sctx->tracked_regs.reg_value[reg+2] != value3 ) {
+
+		radeon_set_context_reg_seq(cs, offset, 3);
+		radeon_emit(cs, value1);
+		radeon_emit(cs, value2);
+		radeon_emit(cs, value3);
+
+		sctx->tracked_regs.reg_value[reg] = value1;
+		sctx->tracked_regs.reg_value[reg+1] = value2;
+		sctx->tracked_regs.reg_value[reg+2] = value3;
+		sctx->tracked_regs.reg_saved |= 7 << reg;
+	}
+}
+
 #endif

src/gallium/drivers/radeonsi/si_state.c

@@ -87,7 +87,8 @@ static void si_emit_cb_render_state(struct si_context *sctx)
 	    (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
 		cb_target_mask = 0;
 
-	radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
+	radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
+				   SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
 
 	/* GFX9: Flush DFSM when CB_TARGET_MASK changes.
 	 * I think we don't have to do anything between IBs.
@@ -111,10 +112,12 @@ static void si_emit_cb_render_state(struct si_context *sctx)
 				  blend->blend_enable_4bit & cb_target_mask &&
 				  sctx->framebuffer.nr_samples >= 2;
 
-		radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
-				       S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
-				       S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
-				       S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
+		radeon_opt_set_context_reg(
+				sctx, R_028424_CB_DCC_CONTROL,
+				SI_TRACKED_CB_DCC_CONTROL,
+				S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
+				S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
+				S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
 	}
 
 	/* RB+ register settings. */
@@ -242,10 +245,11 @@ static void si_emit_cb_render_state(struct si_context *sctx)
 			}
 		}
 
-		radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
-		radeon_emit(cs, sx_ps_downconvert);	/* R_028754_SX_PS_DOWNCONVERT */
-		radeon_emit(cs, sx_blend_opt_epsilon);	/* R_028758_SX_BLEND_OPT_EPSILON */
-		radeon_emit(cs, sx_blend_opt_control);	/* R_02875C_SX_BLEND_OPT_CONTROL */
+		/* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
+		radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
+					    SI_TRACKED_SX_PS_DOWNCONVERT,
+					    sx_ps_downconvert, sx_blend_opt_epsilon,
+					    sx_blend_opt_control);
 	}
 }
 

src/gallium/drivers/radeonsi/si_state.h

@@ -214,6 +214,13 @@ enum si_tracked_reg {
 	SI_TRACKED_DB_RENDER_OVERRIDE2,
 	SI_TRACKED_DB_SHADER_CONTROL,
 
+	SI_TRACKED_CB_TARGET_MASK,
+	SI_TRACKED_CB_DCC_CONTROL,
+
+	SI_TRACKED_SX_PS_DOWNCONVERT, /* 3 consecutive registers */
+	SI_TRACKED_SX_BLEND_OPT_EPSILON,
+	SI_TRACKED_SX_BLEND_OPT_CONTROL,
+
 	SI_NUM_TRACKED_REGS,
 };