i965/urb: Allow blorp to record current settings

This makes it possible to skip urb re-configuration if the
subsequent renders agree with the settings.

Also allows blorp to allocate the maximun amount of vs entries
available. Core upload logic already knows how to calculate this.
Helps one synthetic benchmark.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

src/mesa/drivers/dri/i965/brw_context.h

@@ -1713,16 +1713,8 @@ gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
                               unsigned gs_size, unsigned fs_size);
 
 void
-gen7_emit_urb_state(struct brw_context *brw,
-                    unsigned nr_vs_entries,
-                    unsigned vs_size, unsigned vs_start,
-                    unsigned nr_hs_entries,
-                    unsigned hs_size, unsigned hs_start,
-                    unsigned nr_ds_entries,
-                    unsigned ds_size, unsigned ds_start,
-                    unsigned nr_gs_entries,
-                    unsigned gs_size, unsigned gs_start);
-
+gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
+                bool gs_present, bool tess_present);
 
 /* brw_reset.c */
 extern GLenum

src/mesa/drivers/dri/i965/gen7_blorp.c

@@ -69,18 +69,7 @@ void
 gen7_blorp_emit_urb_config(struct brw_context *brw,
                            const struct brw_blorp_params *params)
 {
-   /* URB allocations must be done in 8k chunks. */
-   const unsigned chunk_size_bytes = 8192;
-   const unsigned urb_size =
-      (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16;
-   const unsigned push_constant_bytes = 1024 * urb_size;
-   const unsigned push_constant_chunks =
-      push_constant_bytes / chunk_size_bytes;
    const unsigned vs_entry_size = gen7_blorp_get_vs_entry_size(params);
-   const unsigned vs_start = push_constant_chunks;
-   const unsigned min_vs_entries = ALIGN(brw->urb.min_vs_entries, 8);
-   const unsigned vs_chunks =
-      DIV_ROUND_UP(min_vs_entries * vs_entry_size * 64, chunk_size_bytes);
 
    if (!(brw->ctx.NewDriverState & (BRW_NEW_CONTEXT | BRW_NEW_URB_SIZE)) &&
        brw->urb.vsize >= vs_entry_size)
@@ -88,19 +77,7 @@ gen7_blorp_emit_urb_config(struct brw_context *brw,
 
    brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
 
-   gen7_emit_urb_state(brw,
-                       min_vs_entries /* num_vs_entries */,
-                       vs_entry_size,
-                       vs_start,
-                       0 /* num_hs_entries */,
-                       1 /* hs_size */,
-                       vs_start + vs_chunks /* hs_start */,
-                       0 /* num_ds_entries */,
-                       1 /* ds_size */,
-                       vs_start + vs_chunks /* ds_start */,
-                       0 /* num_gs_entries */,
-                       1 /* gs_size */,
-                       vs_start + vs_chunks /* gs_start */);
+   gen7_upload_urb(brw, vs_entry_size, false, false);
 }
 
 

src/mesa/drivers/dri/i965/gen7_urb.c

@@ -152,22 +152,66 @@ const struct brw_tracked_state gen7_push_constant_space = {
 };
 
 static void
-gen7_upload_urb(struct brw_context *brw)
+gen7_emit_urb_state(struct brw_context *brw,
+                    unsigned nr_vs_entries,
+                    unsigned vs_size, unsigned vs_start,
+                    unsigned nr_hs_entries,
+                    unsigned hs_size, unsigned hs_start,
+                    unsigned nr_ds_entries,
+                    unsigned ds_size, unsigned ds_start,
+                    unsigned nr_gs_entries,
+                    unsigned gs_size, unsigned gs_start)
+{
+   BEGIN_BATCH(8);
+   OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2));
+   OUT_BATCH(nr_vs_entries |
+             ((vs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
+             (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+   OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2));
+   OUT_BATCH(nr_gs_entries |
+             ((gs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
+             (gs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+   OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2));
+   OUT_BATCH(nr_hs_entries |
+             ((hs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
+             (hs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+   OUT_BATCH(_3DSTATE_URB_DS << 16 | (2 - 2));
+   OUT_BATCH(nr_ds_entries |
+             ((ds_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
+             (ds_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
+   ADVANCE_BATCH();
+}
+
+static void
+upload_urb(struct brw_context *brw)
+{
+   /* BRW_NEW_VS_PROG_DATA */
+   const unsigned vs_size = MAX2(brw->vs.prog_data->base.urb_entry_size, 1);
+   /* BRW_NEW_GEOMETRY_PROGRAM, BRW_NEW_GS_PROG_DATA */
+   const bool gs_present = brw->geometry_program;
+   /* BRW_NEW_TESS_PROGRAMS */
+   const bool tess_present = brw->tess_eval_program;
+
+   gen7_upload_urb(brw, vs_size, gs_present, tess_present);
+}
+
+void
+gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
+                bool gs_present, bool tess_present)
 {
    const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
    const int push_size_kB =
       (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16;
 
    /* BRW_NEW_VS_PROG_DATA */
-   unsigned vs_size = MAX2(brw->vs.prog_data->base.urb_entry_size, 1);
    unsigned vs_entry_size_bytes = vs_size * 64;
    /* BRW_NEW_GEOMETRY_PROGRAM, BRW_NEW_GS_PROG_DATA */
-   bool gs_present = brw->geometry_program;
    unsigned gs_size = gs_present ? brw->gs.prog_data->base.urb_entry_size : 1;
    unsigned gs_entry_size_bytes = gs_size * 64;
 
-   /* BRW_NEW_TESS_PROGRAMS */
-   const bool tess_present = brw->tess_eval_program;
    /* BRW_NEW_TCS_PROG_DATA */
    unsigned hs_size = tess_present ? brw->tcs.prog_data->base.urb_entry_size : 1;
    unsigned hs_entry_size_bytes = hs_size * 64;
@@ -386,40 +430,6 @@ gen7_upload_urb(struct brw_context *brw)
                        brw->urb.nr_gs_entries, gs_size, brw->urb.gs_start);
 }
 
-void
-gen7_emit_urb_state(struct brw_context *brw,
-                    unsigned nr_vs_entries,
-                    unsigned vs_size, unsigned vs_start,
-                    unsigned nr_hs_entries,
-                    unsigned hs_size, unsigned hs_start,
-                    unsigned nr_ds_entries,
-                    unsigned ds_size, unsigned ds_start,
-                    unsigned nr_gs_entries,
-                    unsigned gs_size, unsigned gs_start)
-{
-   BEGIN_BATCH(8);
-   OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2));
-   OUT_BATCH(nr_vs_entries |
-             ((vs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
-             (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
-
-   OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2));
-   OUT_BATCH(nr_gs_entries |
-             ((gs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
-             (gs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
-
-   OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2));
-   OUT_BATCH(nr_hs_entries |
-             ((hs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
-             (hs_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
-
-   OUT_BATCH(_3DSTATE_URB_DS << 16 | (2 - 2));
-   OUT_BATCH(nr_ds_entries |
-             ((ds_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
-             (ds_start << GEN7_URB_STARTING_ADDRESS_SHIFT));
-   ADVANCE_BATCH();
-}
-
 const struct brw_tracked_state gen7_urb = {
    .dirty = {
       .mesa = 0,
@@ -432,5 +442,5 @@ const struct brw_tracked_state gen7_urb = {
              BRW_NEW_TES_PROG_DATA |
              BRW_NEW_VS_PROG_DATA,
    },
-   .emit = gen7_upload_urb,
+   .emit = upload_urb,
 };