Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>tags/17.3-branchpoint
@@ -284,7 +284,7 @@ void r600_context_gfx_flush(void *context, unsigned flags, | |||
if (ctx->is_debug) { | |||
/* Save the IB for debug contexts. */ | |||
radeon_clear_saved_cs(&ctx->last_gfx); | |||
radeon_save_cs(ws, cs, &ctx->last_gfx); | |||
radeon_save_cs(ws, cs, &ctx->last_gfx, true); | |||
r600_resource_reference(&ctx->last_trace_buf, ctx->trace_buf); | |||
r600_resource_reference(&ctx->trace_buf, NULL); | |||
} |
@@ -442,7 +442,7 @@ static void r600_flush_dma_ring(void *ctx, unsigned flags, | |||
} | |||
if (check_vm) | |||
radeon_save_cs(rctx->ws, cs, &saved); | |||
radeon_save_cs(rctx->ws, cs, &saved, true); | |||
rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence); | |||
if (fence) | |||
@@ -464,7 +464,7 @@ static void r600_flush_dma_ring(void *ctx, unsigned flags, | |||
* list in \p saved. | |||
*/ | |||
void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs, | |||
struct radeon_saved_cs *saved) | |||
struct radeon_saved_cs *saved, bool get_buffer_list) | |||
{ | |||
void *buf; | |||
unsigned i; | |||
@@ -482,6 +482,9 @@ void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs, | |||
} | |||
memcpy(buf, cs->current.buf, cs->current.cdw * 4); | |||
if (!get_buffer_list) | |||
return; | |||
/* Save the buffer list. */ | |||
saved->bo_count = ws->cs_get_buffer_list(cs, NULL); | |||
saved->bo_list = CALLOC(saved->bo_count, |
@@ -767,7 +767,7 @@ const char *r600_get_llvm_processor_name(enum radeon_family family); | |||
void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw, | |||
struct r600_resource *dst, struct r600_resource *src); | |||
void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs, | |||
struct radeon_saved_cs *saved); | |||
struct radeon_saved_cs *saved, bool get_buffer_list); | |||
void radeon_clear_saved_cs(struct radeon_saved_cs *saved); | |||
bool r600_check_device_reset(struct r600_common_context *rctx); | |||
@@ -220,6 +220,7 @@ static void si_dump_debug_registers(struct si_context *sctx, FILE *f) | |||
static void si_dump_last_ib(struct si_context *sctx, FILE *f) | |||
{ | |||
int last_trace_id = -1; | |||
int last_ce_trace_id = -1; | |||
if (!sctx->last_gfx.ib) | |||
return; | |||
@@ -233,8 +234,10 @@ static void si_dump_last_ib(struct si_context *sctx, FILE *f) | |||
NULL, | |||
PIPE_TRANSFER_UNSYNCHRONIZED | | |||
PIPE_TRANSFER_READ); | |||
if (map) | |||
last_trace_id = *map; | |||
if (map) { | |||
last_trace_id = map[0]; | |||
last_ce_trace_id = map[1]; | |||
} | |||
} | |||
if (sctx->init_config) | |||
@@ -251,6 +254,12 @@ static void si_dump_last_ib(struct si_context *sctx, FILE *f) | |||
ac_parse_ib(f, sctx->last_gfx.ib, sctx->last_gfx.num_dw, | |||
last_trace_id, "IB", sctx->b.chip_class, | |||
NULL, NULL); | |||
if (sctx->last_ce.ib) { | |||
ac_parse_ib(f, sctx->last_ce.ib, sctx->last_ce.num_dw, | |||
last_ce_trace_id, "CE IB", sctx->b.chip_class, | |||
NULL, NULL); | |||
} | |||
} | |||
static const char *priority_to_string(enum radeon_bo_priority priority) | |||
@@ -845,6 +854,7 @@ static void si_dump_debug_state(struct pipe_context *ctx, FILE *f, | |||
/* dump only once */ | |||
radeon_clear_saved_cs(&sctx->last_gfx); | |||
radeon_clear_saved_cs(&sctx->last_ce); | |||
r600_resource_reference(&sctx->last_trace_buf, NULL); | |||
} | |||
} |
@@ -145,7 +145,9 @@ void si_context_gfx_flush(void *context, unsigned flags, | |||
if (ctx->is_debug) { | |||
/* Save the IB for debug contexts. */ | |||
radeon_clear_saved_cs(&ctx->last_gfx); | |||
radeon_save_cs(ws, cs, &ctx->last_gfx); | |||
radeon_save_cs(ws, cs, &ctx->last_gfx, true); | |||
radeon_clear_saved_cs(&ctx->last_ce); | |||
radeon_save_cs(ws, ctx->ce_ib, &ctx->last_ce, false); | |||
r600_resource_reference(&ctx->last_trace_buf, ctx->trace_buf); | |||
r600_resource_reference(&ctx->trace_buf, NULL); | |||
} | |||
@@ -173,16 +175,16 @@ void si_context_gfx_flush(void *context, unsigned flags, | |||
void si_begin_new_cs(struct si_context *ctx) | |||
{ | |||
if (ctx->is_debug) { | |||
uint32_t zero = 0; | |||
static const uint32_t zeros[2]; | |||
/* Create a buffer used for writing trace IDs and initialize it to 0. */ | |||
assert(!ctx->trace_buf); | |||
ctx->trace_buf = (struct r600_resource*) | |||
pipe_buffer_create(ctx->b.b.screen, 0, | |||
PIPE_USAGE_STAGING, 4); | |||
PIPE_USAGE_STAGING, 8); | |||
if (ctx->trace_buf) | |||
pipe_buffer_write_nooverlap(&ctx->b.b, &ctx->trace_buf->b.b, | |||
0, sizeof(zero), &zero); | |||
0, sizeof(zeros), zeros); | |||
ctx->trace_id = 0; | |||
} | |||
@@ -411,6 +411,7 @@ struct si_context { | |||
/* Debug state. */ | |||
bool is_debug; | |||
struct radeon_saved_cs last_gfx; | |||
struct radeon_saved_cs last_ce; | |||
struct r600_resource *last_trace_buf; | |||
struct r600_resource *trace_buf; | |||
unsigned trace_id; |
@@ -1409,6 +1409,7 @@ void si_trace_emit(struct si_context *sctx) | |||
sctx->trace_id++; | |||
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf, | |||
RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE); | |||
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); | |||
radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) | | |||
S_370_WR_CONFIRM(1) | | |||
@@ -1418,4 +1419,18 @@ void si_trace_emit(struct si_context *sctx) | |||
radeon_emit(cs, sctx->trace_id); | |||
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); | |||
radeon_emit(cs, AC_ENCODE_TRACE_POINT(sctx->trace_id)); | |||
if (sctx->ce_ib) { | |||
struct radeon_winsys_cs *ce = sctx->ce_ib; | |||
radeon_emit(ce, PKT3(PKT3_WRITE_DATA, 3, 0)); | |||
radeon_emit(ce, S_370_DST_SEL(V_370_MEM_ASYNC) | | |||
S_370_WR_CONFIRM(1) | | |||
S_370_ENGINE_SEL(V_370_CE)); | |||
radeon_emit(ce, sctx->trace_buf->gpu_address + 4); | |||
radeon_emit(ce, (sctx->trace_buf->gpu_address + 4) >> 32); | |||
radeon_emit(ce, sctx->trace_id); | |||
radeon_emit(ce, PKT3(PKT3_NOP, 0, 0)); | |||
radeon_emit(ce, AC_ENCODE_TRACE_POINT(sctx->trace_id)); | |||
} | |||
} |