Remove emit_flush() and ILO_RENDER_FLUSH indirections. Signed-off-by: Chia-I Wu <olvaffe@gmail.com>tags/10.4-branchpoint
@@ -323,10 +323,8 @@ draw_vbo(struct ilo_context *ilo, const struct ilo_state_vector *vec) | |||
/* make sure there is enough room first */ | |||
max_len = ilo_render_estimate_size(ilo->render, | |||
ILO_RENDER_DRAW, vec); | |||
if (need_flush) { | |||
max_len += ilo_render_estimate_size(ilo->render, | |||
ILO_RENDER_FLUSH, NULL); | |||
} | |||
if (need_flush) | |||
max_len += ilo_render_get_flush_len(ilo->render); | |||
if (max_len > ilo_cp_space(ilo->cp)) { | |||
ilo_cp_submit(ilo->cp, "out of space"); | |||
@@ -380,8 +378,7 @@ ilo_draw_rectlist(struct ilo_context *ilo) | |||
max_len = ilo_render_estimate_size(ilo->render, | |||
ILO_RENDER_RECTLIST, ilo->blitter); | |||
max_len += ilo_render_estimate_size(ilo->render, | |||
ILO_RENDER_FLUSH, NULL) * 2; | |||
max_len += ilo_render_get_flush_len(ilo->render) * 2; | |||
if (max_len > ilo_cp_space(ilo->cp)) { | |||
ilo_cp_submit(ilo->cp, "out of space"); |
@@ -25,9 +25,11 @@ | |||
* Chia-I Wu <olv@lunarg.com> | |||
*/ | |||
#include "genhw/genhw.h" | |||
#include "intel_winsys.h" | |||
#include "ilo_builder.h" | |||
#include "ilo_builder_render.h" | |||
#include "ilo_render_gen.h" | |||
#include "ilo_render_gen7.h" | |||
#include "ilo_render.h" | |||
@@ -179,3 +181,46 @@ ilo_render_invalidate_builder(struct ilo_render *render) | |||
/* Kernel flushes everything. Shouldn't we set all bits here? */ | |||
render->state.current_pipe_control_dw1 = 0; | |||
} | |||
/** | |||
* Return the command length of ilo_render_emit_flush(). | |||
*/ | |||
int | |||
ilo_render_get_flush_len(const struct ilo_render *render) | |||
{ | |||
int len; | |||
ILO_DEV_ASSERT(render->dev, 6, 7.5); | |||
len = GEN6_PIPE_CONTROL__SIZE; | |||
/* plus gen6_wa_pre_pipe_control() */ | |||
if (ilo_dev_gen(render->dev) == ILO_GEN(6)) | |||
len *= 3; | |||
return len; | |||
} | |||
/** | |||
* Emit PIPE_CONTROLs to flush all caches. | |||
*/ | |||
void | |||
ilo_render_emit_flush(struct ilo_render *render) | |||
{ | |||
const uint32_t dw1 = GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE | | |||
GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH | | |||
GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |||
GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE | | |||
GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |||
GEN6_PIPE_CONTROL_CS_STALL; | |||
ILO_DEV_ASSERT(render->dev, 6, 7.5); | |||
if (ilo_dev_gen(render->dev) == ILO_GEN(6)) | |||
gen6_wa_pre_pipe_control(render, dw1); | |||
gen6_PIPE_CONTROL(render->builder, dw1, NULL, 0, false); | |||
render->state.current_pipe_control_dw1 |= dw1; | |||
render->state.deferred_pipe_control_dw1 &= ~dw1; | |||
} |
@@ -39,7 +39,6 @@ struct ilo_state_vector; | |||
enum ilo_render_action { | |||
ILO_RENDER_DRAW, | |||
ILO_RENDER_FLUSH, | |||
ILO_RENDER_QUERY, | |||
ILO_RENDER_RECTLIST, | |||
}; | |||
@@ -64,8 +63,6 @@ struct ilo_render { | |||
void (*emit_draw)(struct ilo_render *render, | |||
const struct ilo_state_vector *vec); | |||
void (*emit_flush)(struct ilo_render *render); | |||
void (*emit_query)(struct ilo_render *render, | |||
struct ilo_query *q, uint32_t offset); | |||
@@ -172,15 +169,6 @@ ilo_render_emit_draw(struct ilo_render *render, | |||
render->emit_draw(render, vec); | |||
} | |||
/** | |||
* Emit PIPE_CONTROL to flush all caches. | |||
*/ | |||
static inline void | |||
ilo_render_emit_flush(struct ilo_render *render) | |||
{ | |||
render->emit_flush(render); | |||
} | |||
/** | |||
* Emit PIPE_CONTROL or MI_STORE_REGISTER_MEM to save register values. | |||
*/ | |||
@@ -210,4 +198,10 @@ ilo_render_invalidate_hw(struct ilo_render *render); | |||
void | |||
ilo_render_invalidate_builder(struct ilo_render *render); | |||
int | |||
ilo_render_get_flush_len(const struct ilo_render *render); | |||
void | |||
ilo_render_emit_flush(struct ilo_render *render); | |||
#endif /* ILO_RENDER_H */ |
@@ -75,6 +75,9 @@ struct gen6_rectlist_session { | |||
uint32_t CC_VIEWPORT; | |||
}; | |||
void | |||
gen6_wa_pre_pipe_control(struct ilo_render *r, uint32_t dw1); | |||
void | |||
gen6_draw_prepare(struct ilo_render *r, | |||
const struct ilo_state_vector *ilo, | |||
@@ -148,9 +151,6 @@ int | |||
gen6_render_estimate_query_size(const struct ilo_render *render, | |||
const struct ilo_query *q); | |||
void | |||
ilo_render_emit_flush_gen6(struct ilo_render *r); | |||
void | |||
ilo_render_emit_query_gen6(struct ilo_render *r, | |||
struct ilo_query *q, uint32_t offset); |
@@ -60,7 +60,7 @@ gen6_pipe_control(struct ilo_render *r, uint32_t dw1) | |||
/** | |||
* This should be called before PIPE_CONTROL. | |||
*/ | |||
static void | |||
void | |||
gen6_wa_pre_pipe_control(struct ilo_render *r, uint32_t dw1) | |||
{ | |||
/* | |||
@@ -366,7 +366,7 @@ gen6_draw_common_urb(struct ilo_render *r, | |||
* be taking over GS URB space." | |||
*/ | |||
if (r->state.gs.active && !gs_active) | |||
ilo_render_emit_flush_gen6(r); | |||
ilo_render_emit_flush(r); | |||
r->state.gs.active = gs_active; | |||
} | |||
@@ -1471,27 +1471,6 @@ ilo_render_emit_draw_gen6(struct ilo_render *render, | |||
gen6_draw_end(render, vec, &session); | |||
} | |||
void | |||
ilo_render_emit_flush_gen6(struct ilo_render *r) | |||
{ | |||
const uint32_t dw1 = GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE | | |||
GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH | | |||
GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |||
GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE | | |||
GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |||
GEN6_PIPE_CONTROL_CS_STALL; | |||
ILO_DEV_ASSERT(r->dev, 6, 7.5); | |||
if (ilo_dev_gen(r->dev) == ILO_GEN(6)) | |||
gen6_wa_pre_pipe_control(r, dw1); | |||
gen6_PIPE_CONTROL(r->builder, dw1, NULL, 0, false); | |||
r->state.current_pipe_control_dw1 |= dw1; | |||
r->state.deferred_pipe_control_dw1 &= ~dw1; | |||
} | |||
void | |||
ilo_render_emit_query_gen6(struct ilo_render *r, | |||
struct ilo_query *q, uint32_t offset) | |||
@@ -1561,7 +1540,7 @@ ilo_render_emit_query_gen6(struct ilo_render *r, | |||
if (!reg_count) | |||
return; | |||
r->emit_flush(r); | |||
ilo_render_emit_flush(r); | |||
for (i = 0; i < reg_count; i++) { | |||
if (regs[i]) { | |||
@@ -1688,7 +1667,7 @@ gen6_rectlist_commands(struct ilo_render *r, | |||
r->dev->urb_size, 0, blitter->ve.count * 4 * sizeof(float), 0); | |||
/* 3DSTATE_URB workaround */ | |||
if (r->state.gs.active) { | |||
ilo_render_emit_flush_gen6(r); | |||
ilo_render_emit_flush(r); | |||
r->state.gs.active = false; | |||
} | |||
@@ -1973,9 +1952,6 @@ ilo_render_estimate_size_gen6(struct ilo_render *render, | |||
gen6_render_estimate_state_size(render, ilo); | |||
} | |||
break; | |||
case ILO_RENDER_FLUSH: | |||
size = GEN6_PIPE_CONTROL__SIZE * 3; | |||
break; | |||
case ILO_RENDER_QUERY: | |||
size = gen6_render_estimate_query_size(render, | |||
(const struct ilo_query *) arg); | |||
@@ -1997,7 +1973,6 @@ ilo_render_init_gen6(struct ilo_render *render) | |||
{ | |||
render->estimate_size = ilo_render_estimate_size_gen6; | |||
render->emit_draw = ilo_render_emit_draw_gen6; | |||
render->emit_flush = ilo_render_emit_flush_gen6; | |||
render->emit_query = ilo_render_emit_query_gen6; | |||
render->emit_rectlist = ilo_render_emit_rectlist_gen6; | |||
} |
@@ -991,9 +991,6 @@ ilo_render_estimate_size_gen7(struct ilo_render *render, | |||
gen6_render_estimate_state_size(render, ilo); | |||
} | |||
break; | |||
case ILO_RENDER_FLUSH: | |||
size = GEN6_PIPE_CONTROL__SIZE; | |||
break; | |||
case ILO_RENDER_QUERY: | |||
size = gen6_render_estimate_query_size(render, | |||
(const struct ilo_query *) arg); | |||
@@ -1015,7 +1012,6 @@ ilo_render_init_gen7(struct ilo_render *render) | |||
{ | |||
render->estimate_size = ilo_render_estimate_size_gen7; | |||
render->emit_draw = ilo_render_emit_draw_gen7; | |||
render->emit_flush = ilo_render_emit_flush_gen6; | |||
render->emit_query = ilo_render_emit_query_gen6; | |||
render->emit_rectlist = ilo_render_emit_rectlist_gen7; | |||
} |