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i965/vec4: Switch to MOV, not OR, for GS_OPCODE_THREAD_END on Gen8.

Either should work.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
tags/10.3-branchpoint
Kenneth Graunke 11 years ago
parent
commit
17c17b87f9
1 changed files with 3 additions and 4 deletions
  1. 3
    4
      src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp

+ 3
- 4
src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp View File

@@ -202,10 +202,9 @@ gen8_vec4_generator::generate_gs_thread_end(vec4_instruction *ir)

/* Enable Channel Masks in the URB_WRITE_HWORD message header */
default_state.access_mode = BRW_ALIGN_1;
inst = OR(retype(brw_vec1_grf(GEN7_MRF_HACK_START + ir->base_mrf, 5),
BRW_REGISTER_TYPE_UD),
retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
brw_imm_ud(0xff00)); /* could be 0x1100 but shouldn't matter */
inst = MOV(retype(brw_vec1_grf(GEN7_MRF_HACK_START + ir->base_mrf, 5),
BRW_REGISTER_TYPE_UD),
brw_imm_ud(0xff00)); /* could be 0x1100 but shouldn't matter */
gen8_set_mask_control(inst, BRW_MASK_DISABLE);
default_state.access_mode = BRW_ALIGN_16;


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